1. 负责支持模拟产品中的数字模块级及系统级的设计，仿真，验证和逻辑综合
2. 配合后端设计工程从Digital Netlist到GDSII的物理实现
3. 协助完成芯片数字部分芯片测试的相关工作
4. 支持客户进行产品数字功能的Debug
5. 配合模拟工程师，完成模拟功能建模，仿真
1.Responsible for supporting the design, simulation, verification, and logic synthesis of digital modules and system-level in analog products.
2.Collaborate with backend design engineers to achieve physical implementation from Digital Netlist to GDSII.
3.Assist in the completion of chip digital part testing-related work.
4.Support customers in debugging the digital functionality of products.
5.Work with analog engineers to complete the modeling and simulation of analog functions.

1. 电子或计算机类相关专业，本科及以上学历
2. 熟练掌握verilog/verilogaAMS/systemVerilog 至少其中之一
3. 有数模混合IP开发经验者优先
4. 熟练使用常规EDA设计工具和流程
5. 善于主动学习，敢于迎接挑战，优秀的沟通能力及团队合作精神
1.Bachelor's degree or above in Electronic or Computer-related fields.
2.Proficient in at least one of the following: Verilog, VerilogaAMS, or SystemVerilog.
3.Prior experience in the development of mixed-signal IP is preferred.
4.Skilled in the use of common EDA design tools and processes.
5.Proactive in learning, willing to take on challenges, excellent communication skills, and a strong sense of teamwork.