1. Contribute to micro-architecture designs for state-of-the-art high-speed low-power digital IPs.
2. Implement design modules using hardware description language (HDL).
3. Design schemes for multi-clock domain crossing and synchronization.
4. Drive OVM/UVM design verification and support FPGA engineers for early prototyping.
5. Execute RTL-to-GDS development flow, including synthesis, schematics design, and supervising custom layout.
6. Check timing closure, and analyze the performance/power/area of designed IPs.
7. Support IP integration to SoC, including soft-IP RTL integration and hard-IP GDS macro integration.
8. Perform post-layout Hspice simulation to characterize the designed circuit.
9. Assist with test program development, chip bring-up, validation, and production maturity.

1. Master’s degree in Electrical Engineering/Computer Science.
2. 6 months experience as an ASIC Design Engineer or Verification Design Engineer.
3. Proficient with Verilog, SystemVerilog, and Python or Perl.
4. Strong knowledge of micro-architecture design, function modeling, RTL coding, and SoC Integration.
5. Good at multi-clock domain designs, timing analysis, and optimization.
6. Experience in SystemVerilog OVM/UVM, synthesis, mixed-signal circuit schematics design, and layout design.
7. Able to proactively take on responsibilities and competent to work in a start-up environment.