1.Chip micro-architecture design and Verilog RTL design for high-performance storage products.
2.Participate in complete ASIC design flow, including SoC architecture design, implementation, verification, synthesis, and chip bring-up.
3.Work with SoC architects and firmware engineers to explore new architecture and to optimize system design.
4.Prepare detailed design specifications of sub-blocks for the next generation NAND flash controller.
5.Design and build block-level test benches to perform block-level verification, and ensure the correctness of the desired functional blocks.
6.Perform design integration, logic synthesis, and design optimization for timing, area and power for given function blocks or sub-systems for data storage applications.
7.Analyze and resolve issues with verification, firmware and validation team.
1.负责高性能存储类芯片微架构设计和Verilog RTL设计；
2.参与芯片设计的整个流程，芯片架构设计实现，并解决验证，综合和芯片调试中发现的设计问题；
3.与芯片架构师，固件工程师合作，实现新一代芯片架构设计及软硬件调试；
4.参与下一代SSD主控芯片关键模块的功能制定与设计，撰写完整的设计规格文档
5.设计并开发基于模块化的测试脚本和环境，并对所负责的模块进行功能测试与验证，确保子模块的设计正确性
6.参与SOC芯片的后端集成，对负责的子模块进行逻辑综合，时序分析，并持续优化时序，面积和功耗，确保整体SOC芯片设计的最优化
7.与验证团队，固件开发团队和测试团队合作，分析和解决产品中的问题。

1.B.S. or above in EE/CE/CS or related engineering discipline with 3+ years ASIC design experience.
2.Hands-on experience in digital circuit design and implementation. Proficient in Verilog/System Verilog coding. Familiar with at least one of script languages, e.g. shell/tcl/perl/makefile/python.
3.Solid knowledge of ECC algorithm, such as LDPC, BCH etc.is preferred.
4.Solid knowledge of encryption/decryption algorithm, such as AES, SM4 etc.is preferred.
5.Solid knowledge of NAND interface protocols, such as ONFI, TOGGLE etc.is preferred.
6.Experience of SSD storage controller development is preferred.
7.Knowledge of synthesis (DC), STA, Formal check, CDC flow is a plus.
8.Self-motivation, teamwork and good communication skills are essential.
9.Proficient in both written and verbal English.
10.Knowledge of UVM is a plus.
1.电子工程、通讯、微电子或相关专业本科及以上，有3年以上工作经验;
2.熟悉或精通ASIC设计全流程
3.精通各种数字设计技能、Verilog/System Verilog设计语言。了解一种或几种脚本语言，如shell/tcl/perl/make/python等；
4.熟悉LDPC BCH等纠错算法优先；
5.熟悉AES SM4等加解密算法优先；
6.熟悉ONFI TOGGLE等NAND接口协议优先；
7.有SSD Controller控制器领域设计经验者优先；
8.熟悉综合（DC），STA，Formal Check，CDC设计流程者优先；
9.具有较强的责任感，学习能力和团队合作能力；
10.具备中英文读写能力和良好的沟通能力。