1.参与先进DDR/NAND interface IP设计, 定义功能模块。
2.参与功能模块的RTL Verilog代码编写与验证。
3.负责设计基于先进制程standardcell的数字电路。
4.负责数字电路和RTL model的一致性验证，timing closure。
5.与SoC团队密切合作，确保IP模块能被正确使用与整合。
6.与后端团队密切合作，辅助IP模块的layout设计。
7.与模拟团队密切合作，确保模拟IP能被正确使用与整合。
8.使用后端仿真工具完成基于layout的timing closure及其他物理验证。

1.计算机工程、电气工程、计算机科学或相关领域的学士或硕士学位。
2.熟练掌握Verilog及前端验证EDA工具。
3.熟练使用Cadence Virtuoso完成电路设计。
4.对电路timing closure有深入了解，能够对timing violation提出解决方案。
5.熟练掌握Hspice等电路级仿真工具。
6.熟悉DDR或NAND接口者优先。
7.强大的问题解决能力，出色的沟通能力，能够在协作的团队环境中有效工作。

1.Chip micro-architecture design and Verilog RTL design for high-performance storage products.
2.Participate in complete ASIC design flow, including SoC architecture design, implementation, verification, synthesis, and chip bring-up.
3.Work with SoC architects and firmware engineers to explore new architecture and to optimize system design.
4.Prepare detailed design specifications of sub-blocks for the next generation NAND flash controller.
5.Design and build block-level test benches to perform block-level verification, and ensure the correctness of the desired functional blocks.
6.Perform design integration, logic synthesis, and design optimization for timing, area and power for given function blocks or sub-systems for data storage applications.
7.Analyze and resolve issues with verification, firmware and validation team.
1.负责高性能存储类芯片微架构设计和Verilog RTL设计；
2.参与芯片设计的整个流程，芯片架构设计实现，并解决验证，综合和芯片调试中发现的设计问题；
3.与芯片架构师，固件工程师合作，实现新一代芯片架构设计及软硬件调试；
4.参与下一代SSD主控芯片关键模块的功能制定与设计，撰写完整的设计规格文档
5.设计并开发基于模块化的测试脚本和环境，并对所负责的模块进行功能测试与验证，确保子模块的设计正确性
6.参与SOC芯片的后端集成，对负责的子模块进行逻辑综合，时序分析，并持续优化时序，面积和功耗，确保整体SOC芯片设计的最优化
7.与验证团队，固件开发团队和测试团队合作，分析和解决产品中的问题。

1.B.S. or above in EE/CE/CS or related engineering discipline with 3+ years ASIC design experience.
2.Hands-on experience in digital circuit design and implementation. Proficient in Verilog/System Verilog coding. Familiar with at least one of script languages, e.g. shell/tcl/perl/makefile/python.
3.Solid knowledge of ECC algorithm, such as LDPC, BCH etc.is preferred.
4.Solid knowledge of encryption/decryption algorithm, such as AES, SM4 etc.is preferred.
5.Solid knowledge of NAND interface protocols, such as ONFI, TOGGLE etc.is preferred.
6.Experience of SSD storage controller development is preferred.
7.Knowledge of synthesis (DC), STA, Formal check, CDC flow is a plus.
8.Self-motivation, teamwork and good communication skills are essential.
9.Proficient in both written and verbal English.
10.Knowledge of UVM is a plus.
1.电子工程、通讯、微电子或相关专业本科及以上，有3年以上工作经验;
2.熟悉或精通ASIC设计全流程
3.精通各种数字设计技能、Verilog/System Verilog设计语言。了解一种或几种脚本语言，如shell/tcl/perl/make/python等；
4.熟悉LDPC BCH等纠错算法优先；
5.熟悉AES SM4等加解密算法优先；
6.熟悉ONFI TOGGLE等NAND接口协议优先；
7.有SSD Controller控制器领域设计经验者优先；
8.熟悉综合（DC），STA，Formal Check，CDC设计流程者优先；
9.具有较强的责任感，学习能力和团队合作能力；
10.具备中英文读写能力和良好的沟通能力。

负责公司SSD产品的日常固件测试，提交和跟进测试BUG以及测试报告等；
搭建SSD产品测试环境，编写测试用例和方案，完成SSD测试流程；
负责自动化测试软件用例的开发及维护，并不断优化；
对测试中发现的问题进行详细分析和准确定位，重现和归纳问题并及时给出现场解决方案；
配合固件研发和硬件团队跟踪故障并修复；
协助项目经理进行产品/项目测试进度的控制及测试任务跟踪；
对测试规范、流程、方法、技术持续改进。

全日制本科及以上学历，计算机、电子电气、通信工程等相关专业；
三年以上软硬件测试及故障定位经验，熟悉软件系统测试理论方法；
熟悉 Linux 平台下的相关测试工具，能够熟练的编写shell/Python脚本；
具备独立实现测试脚本设计编写能力或测试框架设计能力；
以下为知识技能加分项：
具备SSD产品故障分析和解决问题的经验；
熟悉PCIe/NVMe/SATA协议；
熟悉SSD内部算法、NAND基本工作原理。
有较强的逻辑思维能力、分析判断能力以及高效的执行力；
勤奋踏实的工作态度，责任心强，能够积极主动地处理问题；
具备较强的抗压能力，较好的沟通和团队协作精神。

岗位职责：
1.负责产品客户使用过程中出现的失效分析工作，找到根因并输出失效分析报告；
2.客户线上产品故障跟踪，不良率统计，监控市场表现数据，深入分析售后故障；
3.负责代工厂生产工序不良品分析，快速解决产线失效问题，根据不良产品产生的原因，与生产测试团队一起完善测试程序和测试方法等变更，提升产品测试的可靠性和检测能力；
4.与设计部门合作，根据产品失效原因给出改进措施，并对不良原因给出预防措施和改善方案，进行闭环落地；
5.与工具组和测试组合作，开发分析工具，优化流程，提高效率。

1.通信、电子、电力等相关专业本科及以上学历；
2.三年以上电子产品失效分析经验，熟练使用分析维修工具，如风枪、烙铁、示波器等，对电子产品的失效分析有丰富的实操经验；
3.具备数字电路、模拟电路等基本知识，可看懂电路图，能够独立分析产品电路；
4.有一定的器件基础，熟悉电路基础知识，常见的电子元器件以及封装；
5.掌握SSD的测试软件和PA， LA， 示波器等仪器；
6.掌握8D分析流程；
7.能承受较强的工作压力，能接受工作需要短期出差；
8.心态积极，乐于学习，有团队合作精神，执行力强，善于沟通。

1.代表SoC团队负责支持公司内部固件团队和客户进行SSD主控芯片的SDK和FTK开发。
2.深入了解SSD主控芯片的原理和功能，提供芯片在应用及性能相关的固件配置和解决方案，协助解决内部固件团队和客户遇到的芯片相关问题。
3.分析测试结果并完成测试报告，跟踪SoC问题，主导产品手册和应用指南的撰写，确保文档的准确性和完整性。
4.根据研发目标定义芯片的测试规范，制定测试计划和方案，搭建测试平台，完成测试任务。
5.协助分析和解决ATE测试中的硬件问题。
6.负责芯片在系统中的应用支持，配合芯片工程师进行芯片RTL仿真，问题复现和调试工作。
7.负责SSD产品导入客户应用平台，分析并解决客户在产品导入和使用过程中遇到的技术问题。
8.配合FAE团队和售后团队为客户提供技术支持，包括问题诊断、解决方案建议及产品优化，确保客户满意度。

1.本科及以上学历，电子工程、微电子或相关专业，5～7年相关工作经验。
2.熟悉相关软硬件电路设计和调试方法，具备PCIe、NVMe、DDR、LPDDR协议，RISC-V，规范，设计，验证和实现的技术知识。
3.熟悉相关实验室测试仪器操作，如协议分析仪、示波器、信号发生器和万用表等。
4.具有ASIC HDL设计经验，熟悉仿真和/或验证。
5.具备在ASIC/SoC设计的IP设计或集成流程中的一个或多个环节的经验（如仿真/验证、RTL综合、时序收敛等），或在系统环境中的硅后调试经验。
6.具备一定的英语沟通、阅读和书写能力；拥有扎实的电路、信号与系统或控制原理基础。
7.具有积极主动的工作态度和优秀的团队协作精神，具备良好的分析能力、解决问题能力和描述问题的能力。
8.具有抗压能力、责任心和适应性强，必要时能够出差现场支持。

Looking for a talented and highly self-motivated candidate that has strong background and hands-on experience in the physical design for advanced technology nodes. The candidate will work on the physical implementation of our state-of-art SoC products. Driving all aspects from RTL to GDS including timing and physical trade-offs, die size reduction and delivery of final product on schedule while meeting design goals.
Responsibilities:
1.Perform physical implementation of the ASIC design from netlist to GDS, including floorplanning, power grid and clock network implementation, place and route, timing closure and physical verification.
2.Work with multiple teams on the SoC architecture study and timing/power/area design target.
3.Working with different IP owners to ensure seamless IP integration at full chip level.
4.Writing scripts for design automation flow and productivity enhancement.
工作职责：
1.负责芯片从网表到GDS的后端物理实现，包括布局规划，时钟树生成（CTS）， 布局布线，时序优化和收敛，以及GDS的物理验证。
2.和多个设计团队合作制定芯片结构，参与制定芯片性能/面积/功耗等方面的设计目标。
3.与不同功能模块的设计团队合作保证功能模块的顺利集成。
4.优化后端设计自动化的流程和提高团队设计开发效率。

Job Requirement:
1,Experience in ASIC Physical Design from netlist to GDSII.
2.Experience in using EDA tools such as Synopsys ICC or Cadence SOC Encounter.
3.Hands on experience in Floor planning, CTS, STA.
4.Experience in Power grid, clock tree, and low-power flow implementation methods.
5.Hands on experience with STA using Primetime, power analysis.
6.Hands on experience with IR drop analysis, formal verification and physical verification.
7.Timing closure, ECO process using PrimeTime.
8.Programming and scripting skills (Tcl, perl ,shell).
9.DFT/DFM knowledge is a plus.
10.Self-motivated and able to work effectively in a start-up environment.
11.Ability to execute to stringent schedule & die size requirements and effective communication skills.
任职要求
1.后端工作经验，微电子或者相关学科本科以上学历，欢迎本科的小伙伴。
2.良好的沟通能力和团队精神，能够在精干的团队环境里高效率的发挥自己的能力。
3.熟练使用主流P&R流程工具（Synopsys、Cadence的相关P&R工具）。
4.具有从netlist到GDS整个流程的实际经验，包括布局规划，power gird，时钟树生成(CTS)，布局布线设计，时序收敛，IR-drop，lvs/drc。
5.具备扎实的时序分析知识与signoff的技能。
6.具备DFT/DFM相关经验的优先。
7.熟练的脚本编写技能（Tcl，perl, shell)。

1. Contribute to micro-architecture designs for state-of-the-art high-speed low-power digital IPs.
2. Implement design modules using hardware description language (HDL).
3. Design schemes for multi-clock domain crossing and synchronization.
4. Drive OVM/UVM design verification and support FPGA engineers for early prototyping.
5. Execute RTL-to-GDS development flow, including synthesis, schematics design, and supervising custom layout.
6. Check timing closure, and analyze the performance/power/area of designed IPs.
7. Support IP integration to SoC, including soft-IP RTL integration and hard-IP GDS macro integration.
8. Perform post-layout Hspice simulation to characterize the designed circuit.
9. Assist with test program development, chip bring-up, validation, and production maturity.

1. Master’s degree in Electrical Engineering/Computer Science.
2. 6 months experience as an ASIC Design Engineer or Verification Design Engineer.
3. Proficient with Verilog, SystemVerilog, and Python or Perl.
4. Strong knowledge of micro-architecture design, function modeling, RTL coding, and SoC Integration.
5. Good at multi-clock domain designs, timing analysis, and optimization.
6. Experience in SystemVerilog OVM/UVM, synthesis, mixed-signal circuit schematics design, and layout design.
7. Able to proactively take on responsibilities and competent to work in a start-up environment.

1. 负责支持模拟产品中的数字模块级及系统级的设计，仿真，验证和逻辑综合
2. 配合后端设计工程从Digital Netlist到GDSII的物理实现
3. 协助完成芯片数字部分芯片测试的相关工作
4. 支持客户进行产品数字功能的Debug
5. 配合模拟工程师，完成模拟功能建模，仿真
1.Responsible for supporting the design, simulation, verification, and logic synthesis of digital modules and system-level in analog products.
2.Collaborate with backend design engineers to achieve physical implementation from Digital Netlist to GDSII.
3.Assist in the completion of chip digital part testing-related work.
4.Support customers in debugging the digital functionality of products.
5.Work with analog engineers to complete the modeling and simulation of analog functions.

1. 电子或计算机类相关专业，本科及以上学历
2. 熟练掌握verilog/verilogaAMS/systemVerilog 至少其中之一
3. 有数模混合IP开发经验者优先
4. 熟练使用常规EDA设计工具和流程
5. 善于主动学习，敢于迎接挑战，优秀的沟通能力及团队合作精神
1.Bachelor's degree or above in Electronic or Computer-related fields.
2.Proficient in at least one of the following: Verilog, VerilogaAMS, or SystemVerilog.
3.Prior experience in the development of mixed-signal IP is preferred.
4.Skilled in the use of common EDA design tools and processes.
5.Proactive in learning, willing to take on challenges, excellent communication skills, and a strong sense of teamwork.

1.面向Tier1s and OEMs推广和销售公司的存储控制器芯片和固态硬盘解决方案；
2.参与项目的生命周期管理，通过与内部全球团队合作解决客户问题，直至客户成功推出产品；
3.收集、分析行业及市场应用状况，促进公司产品的更迭与发展，针对竞争环境及时调整营销策略；
4.挖掘客户需求，策划销售活动，推动商务谈判，参与项目招投标的过程管控，最终实现产品销售；
5.控制销售预算、销售成本，与销售目标平衡发展，合理配置与使用公司资源。

1.本科及以上学历，计算机、电子工程，自动化等相关理工科专业；
2.3-5年销售经验，熟悉半导体芯片行业和电子产品市场，熟悉NAND闪存和主流SSD存储主控厂商产品及解决方案；
3.有客户资源优先，能独立挖掘优质代理商及终端客户；
4.目标导向，有较强的系统化思维和自驱力；
5.具备良好的沟通协调能力、应变能力，有良好的服务意识和团队合作精神；
6.有创业精神，乐于接受挑战，具备较强的抗压能力；
7.认同企业文化，秉持公司价值观，遵从公司营销管理制度。

1.Lead supports the establishment of SSD module program goals and prioritizes deliverables. Heavily contribute to program managing and reporting to achieve overall program objectives with quality.
2.Cross-functional communication between internal project teams, work with engineering.
management to manage the execution of the plan of record (e.g., on time, on budget, within scope). Enable the development effort by creating and monitoring an efficient, streamlined process, provide timely issue resolution and critical path management.
3.Define various checklist and manage the quality for each major milestone closer. Follow up with team on pending actions items and get the timely closer. Motivate and encourage team members to execute their task flawlessly by creating influence and not via authority.
4.Identify risk and gaps. Tracks all key metrics pertaining to a program, provides early warning for potential metric deviations and escalates in timely manner.
5.Drive, manage and follow up weekly status meeting with core team, extended team and executives and keep everyone on sync.
6.Supports the compliance of processes by following best practices and procedures.

Key Qualifications
1.Minimum BE/BS degree (Masters preferred) in Electrical/Electronic Engineering with 5+ years of practical experience in program management.
2.Have general knowledge on product development life cycle (Proto build, EVT, DVT etc.) and strong fundamentals for multiple programs/technology by applying up-to-date program management knowledge to meet deadlines.
3.Able to complete tasks with multiple steps that can be performed in various orders; some planning and prioritization must occur to complete the tasks effectively.
4.Able to influence technical team and executive on making right decision without having a direct report.
Minimum Qualifications
1.Engineering build schedule planning.
2.Hosting regular meeting / review with X-functional team.
3.Familiar with technical risk assessment review.
4.Good in writing status report & technical review summary.
5.Good problem analytic skill.
6.Good status tracking skill and attend to detail.
7.Able to work well with cross cultural and multi-functional team.
Technical (Good to have)
1.Problem solving methodology / tool.
2.Failure analysis (FA tool) .
3.New production line Equipment / tester bring up.
4.Production line Quality contro